With the continuous advancement and development in the semiconductor manufacture to ultra large semiconductor integration (ULSI), the performance of MOS devices can not be promoted effectively due to the scales of these devices are getting smaller. And on the other hand, the process for manufacturing these shrinkage devices are also getting more difficult. Especially when the scales getting under 0.25 .mu.m, some deficiencies unapparent at the original large scale will be magnified, and reduce the yields and reliabilities of the manufactured devices. For example, the edge profile of shallow trench isolation (STI) used to divide the active areas in the semiconductor process will result in leakage currents of the MOS devices formed on the active areas.
Please refer to FIG. 1, a top view of the semiconductor wafer in related process is illustrated. A rectangle structure 10 made of polysilicon is used to serve as a gate structure of a MOS devices. And another rectangle structure 12 is used to serve as the active area (AA) for defining the MOS devices. It is noted that a source and a drain structure is defined in the rectangle structure 12 not covered by the gate structure 10 for a transistor structure. Thus a length L of the gate structure 10 in FIG. 1 is used to define the channel length of the manufactured transistor device. And the width W of the rectangle area 12 can be used to define the width of the transistor device.
Then, referring to FIG. 2, the cross section view of the semiconductor wafer along the line B--B' of the FIG. 1 is shown. The full view of the transistor structure is apparently illustrated, wherein the gate structure 10 is located on the semiconductor substrate 14. The source region 16 and the drain region 17 are defined in the semiconductor substrate 14 adjacent to the gate structure 10. The distance between the source region 16, through the gate structure 10, to the drain region 17 is equal to the length 12L of the active area 12 in FIG. 1.
Referring to FIG. 3, the cross section view of the semiconductor wafer along the line A--A' of the FIG. 1 is illustrated. As described above, the gate structure 14 is on the top surface of the semiconductor substrate 14. And two shallow trench isolations are formed in the semiconductor substrate 14 to define the active area for manufacturing the transistor device, wherein the width 12W between the two isolations is equal to the width W of the active area 12 shown is FIG. 1. In general, the MOS device is defined with the gate structure 10 in the active area 12 and substrate 14, so the shallow trench isolations 18, the substrate 14 therein, and the gate structure 10 all can influence the performance of the MOS device.
Notedly, following the shrinkage scales of the semiconductor devices, the ratio (W/L) of the width W of the active area to the length L of the transistor channel is getting to 2:1 now from the value 10:1 of conventional technique. Namely the active area used to contain a MOS device is also getting smaller due to the scale shrinkage of devices, and reduces the ratio of W/L. However, following the lower ratio of W/L, the profiles of the junctions between the substrate 14 and the shallow trench isolations 18 will cause enormous influence to the manufactured transistor devices. For example, the corner profile in the junction area 20 of the substrate 14 will result in the electrical field thereof more crowded and bring about the tip discharge effect. On the other hand, the parasitic corner transistors will be formed in the junction area 20 at the edges of the active area 12, thus the current leakage and sub-threshold leakage will occur therein.
The proposal of forming doping areas in the sidewalls and the bottoms of trench structures is provided to overcome the issue above in by Liaw in U.S. Pat. No. 5,960,276. As shown in FIG. 4, a thin oxide layer 21 is formed on the top surface of the trench structure defined on a semiconductor substrate 14. Then an ion-implanting procedure is performed to form the doping areas in sidewalls and bottom of the trench. For the portions of sidewalls and bottom located in the P-well, the doping area 22 is with P-type dopants. Similarly the doping area 24 with N-type dopants is defined in the portions of sidewall and bottom located in the N-well of the substrate 14. Thus, the crowded electrical field on the junction between the active area and the trench isolation structure can be reduced, and the probability of sub-threshold leakage occurring can be lowered.
However, when the doping area, as described above, is defined in sidewalls and bottom of the trench structure, the P-type doping area 22 and the N-type doping area 24 contact with each other in the junction between the N-well and the P-well as shown in FIG. 4. Thus, the depletion region between the N-well and the P-well will be lowered to cause the leakage occurring on the junction between the N-well and the P-well.